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The complete hardware security solution.

A Crypto Coprocessor is a dedicated hardware module that accelerates cryptographic operations on a device and provides a reliable foundation to build a security sub-system on a chip.

They are embedded within an SoC and include multiple hardware security measures to protect the chip from reverse-engineering, physical tampering, and supply chain counterfeiting threats. Crypto Coprocessors require both hard (GDS) and soft (RTL) macros to create a secure boundary for cryptographically secure processing. They offload those operations from the main CPU that require cryptographic algorithms to free up the CPU for other functions, as well as help accelerate secure data operations, including both symmetric and asymmetric ciphers. This allows the added benefit of keeping all plaintext data within the secure boundary, removing the vulnerabilities associated with leaving private data on a shared-use system bus.

Crypto coprocessors need to protect against a wide array of invasive, semi-invasive, and non-invasive attacks by providing anti-tampering protection by detecting and containing attacks, followed by the automatic Zeroization of sensitive data.

As seen in the above figure, crypto coprocessors need to protect against a wide array of invasive, semi-invasive, and non-invasive attacks by providing anti-tampering protection by detecting and containing attacks, followed by the automatic Zeroization of sensitive data. They also establish a protected Hardware Root of Trust during the Secure Boot phase to authenticate each stage of the bootup process – including the chip, BIOS, bootloader, operating system, and all subsequent applications the device is required to run.

Today, Crypto Coprocessors are already widely deployed in everything from missiles to smart cards. They will become even more prevalent in the future, with the continuing adoption of modern confidential computing standards that require crypto coprocessors, such as TPM 2.0 – taking its place as an essential IP block for chip design.