NeoPUF creates entropy in two parallel transistors based on quantum tunneling mechanism (Refer to PUFSeries 3). The concept is like flipping a coin to determine the chances of heads and tails. The high voltage will be applied to NeoPUF until one of the oxides begins to have a tunneling current which determines an output value of either 0 or 1. Since each bit is an effective static entropy, NeoPUF can easily achieve an entropy pool of any capacity. We could exam the randomness of NeoPUF by using the min-entropy analysis from NIST 800-90B; its value is 0.988 and perfectly fits the IID characteristics. On the other hand, SRAM PUF often has process dependency problems, such as even-odd bit lines, even-odd word lines, or special dependencies (WL\/BL Even-Odd or Pattern effect), which are unavoidable in the semiconductor manufacturing processes. SRAM PUFs also requires additional pre-screening and post-processing procedures for error correction. <\/p>\n\n\n\n
How do you judge whether a PUF is truly random? Is it affected by sample size? Figure 1 illustrates the relationship between Hamming Weight (HW) and key length. The area between the blue and red curves represents a reasonable HW (3sigma confidence level) distribution. Using a 128-bit key length as an example, there is a 99.7% chance that the samples will obtain a hamming distance of 37% to 63%. <\/p>\n\n\n\n
Based on this theory, examining PUFs from a different perspective will lead to an interesting question given that a 128-bit PUF value is arbitrarily obtained, can we determine whether the PUF is truly random or non-random based on the Hamming weight result? The answer is hard to judge. Obviously, the PUF length is too short and the entropy pool is too small. Therefore, it impossible to obtain effective min-entropy analysis and effectively evaluate whether the sequence is truly random or not. In contrast, if the PUF entropy pool of each chip is 2048 bits or higher (such as NeoPUF), the randomness can be easily evaluated by statistical sampling methods, allowing it to be easily implemented in the chip. <\/p>\n\n\n
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II. True Hardware <\/strong><\/p>\n\n\n\n A true hardware root of trust is preferably created from pure hardware. If it uses a PUF that requires software assistance (such as SRAM PUF), there are several hidden caveats: <\/p>\n\n\n\n For NeoPUF, which is generated by pure hardware, both the entropy source and the original key can be prepared in micro-sec. It does not require additional software support, thereby reducing test time and system security risks, as well as making it relatively easy to design into chips. <\/p>\n\n\n\n III. Security <\/strong><\/p>\n\n\n\n Complete security must fully consider the system\u2019s ability to resist invasive, semi-invasive, and non-invasive attacks during the power-on and power-off stage. <\/p>\n\n\n\n Power-Off: The principle of generating NeoPUF is based on creating an entropy source caused by a current tunneling through the gate oxide. In other words, there is no actual key information stored and therefor no physical traces. Of course, the design layout including the arrangement of the element array and the related circuit require a complete design set to ensure the reliability of the overall security mechanism. <\/p>\n\n\n\n Power-on: During the key generation process of the entire security module, it is necessary to strengthen the electrical protection when reading PUF value. Hackers may attack the system by targeting or using data IO, control signal, and power consumption analysis. That is why a complete high-standard security design should include the features and function designs as shown in Table 1. <\/p>\n\n\n\n Table 1. The Anti-Tampering Features of NeoPUF <\/strong> <\/p>\n\n\n IV. Mass Production<\/strong><\/p>\n\n\n\n \u201cSecurity\u201d should not only be regarded as an \u201cadded value\u201d. Even if the security functions only occupy a small area in chip deployment (<0.1mm2), its yield performance and life cycle are also important. Therefore, PUF must be able to ensure that the bit error rate is greatly reduced in the pre-screening process during the mass production stage. Furthermore, the test process must ensure that the range of the bit error rate under various temperature, environment, and process variations are within the capability of the error correction circuit. It is necessary to predict the changes of the bit error rate of the entire component in the product life cycle. A PUF-based security design should not only be a \u201cfunction\u201d, but also a complete product that promises yield and reliability so that we could say it meets the qualification to proceed to the mass production. <\/p>\n\n\n\n In conclusion, the complete security designs of eMemory\u2019s NeoFuse and NeoPUF have passed third-party security certifications, which also ensures that clients can enjoy high security performance and yield during mass production. We believe that only when clients really apply the complete security design to mass-production and product applications can there be a win-win situation for IP suppliers and SoC manufacturers. <\/p>\n\n\n\n V. Reference Materials and Sources <\/strong><\/p>\n\n\n\n [1]\u00a0PUF Series 1: SRAM PUF is Increasingly Vulnerable<\/a>\u00a0<\/p>\n\n\n\n [2]\u00a0PUF Series 2: NeoPUF, A Reliable and Non-traceable Quantum Tunneling PUF<\/a>\u00a0<\/p>\n\n\n\n [3] PUF Series 3: The Quantum Tunneling Mechanism of NeoPUF<\/a> <\/p>\n\n\n\n [4]\u00a0PUF Series 4: Why a True Hardware PUF is more Reliable as RooT of Trust<\/a>\u00a0<\/p>\n\n\n\n\n
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